1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high speed bipolar transistor having super self-aligned process technology (SST) structure.
2. Description of the Prior Art
A bipolar transistor having the SST structure designed for increasing the operating speed of a vertical bipolar transistor has been put to practical use. An NPN bipolar transistor with this structure can be formed as described in the following. First, an N-type epitaxial layer which is made selectively into a collector region and a device isolation region are formed on the surface of a P-type silicon substrate. Following that, a P.sup.+ -type polycrystalline silicon film is formed allover the surface, and a base lead-out electrode and an emitter opening consisting of P.sup.+ -type polycrystalline film are formed by etching the P.sup.+ -type polycrystalline film. Next, a P.sup.+ -type extrinsic base region is formed on the surface of the N-type epitaxial layer in self-aligned manner with respect to the base lead-out electrode, and a P-type intrinsic base region of the N-type epitaxial layer is formed in self-aligned manner with respect to the emitter opening. A spacer consisting of an insulating film is formed on the side face of the emitter opening. Then, an emitter lead-out electrode consisting of an N.sup.+ -type polycrystalline silicon film is formed in the form of buried in the emitter opening, and an N.sup.+ -type emitter region is formed on the surface of the P-type intrinsic base region in self-aligned manner with respect to the emitter lead-out electrode. This bipolar transistor is realizing high operating speed by reducing the parasitic base resistance and the parasitic base capacitance.
In order to further increase the operating speed of the bipolar transistor of this structure two technical issues have to be solved. A first issue is that it is difficult to further reduce the parasitic base resistance due to the presence of the high resistance P-type intrinsic base region between the N.sup.+ -type emitter region and the P.sup.+ -type extrinsic base region. A second issue is that degradation in the breakdown voltage of the emitter region, increase in the leakage current, fluctuation of the current amplification factor (h.sub.FE) or the like, for example, become liable to occur, caused by the etching of the P.sup.+ -type polycrystalline silicon film for the formation of the emitter opening.
In accordance with Japanese Laid-Open Patent Application No. 1-144679 (laid open on Jun. 6, 1989) by the present applicant, the aforementioned first issue can be settled by providing a P-type link base region which connects the two regions of N.sup.+ -type emitter region and the P.sup.+ -type extrinsic base region in the fabrication of a bipolar transistor of the above-mentioned structure. The impurity concentration of the P-type link base region is lower than the impurity concentration of the P.sup.+ -type extrinsic base region, and is higher than the impurity concentration of the P-type intrinsic base region. The P-type link base region is realized by forming a spacer consisting of a BSG film on the side face of the emitter opening and inducing diffusion of boron from the spacer.
However, the second issue cannot be settled by the fabrication method disclosed in the aforementioned provisional publication. The reasons for this are as follows. In the region where the emitter opening is formed, the P.sup.+ -type polycrystalline silicon film is brought into direct contact with the N-type epitaxial layer. Because of this, it is very difficult in the etching (this being a dry etching such as RIE which is highly anisotropic) of the P.sup.+ -type polycrystalline silicon film for the formation of the emitter opening to stop the etching at the interface of the P.sup.+ -type polycrystalline silicon film and the N-type epitaxial layer. As a result, the surface of the N.sup.+ -type epitaxial layer where the emitter region is formed is roughened by the removal of the surface by etching, causing deterioration of the breakdown voltage of the emitter region, increase in the leakage current, fluctuation of the current amplification factor (h.sub.FE) or the like. It should be mentioned that even if the above-mentioned etching is done in wet mode (isotropic etching), roughening due to scraping of the N-type epitaxial layer where the emitter region is formed is inevitable. In particular, fine emitter opening can no longer be obtained in this case because of the side etching of the P.sup.+ -type polycrystalline silicon film.
The second issue can be settled to a certain extent by the fabrication method of bipolar transistor disclosed in Japanese Patent Application Laid-Open No. 64-64258 (laid open on Mar. 10, 1989). This fabrication method is as described below.
First, a field oxide film is formed selectively on the surface of an N-type silicon substrate excluding at least the region where a P.sup.+ -type extrinsic base region and the region where a base region consisting of a P-type intrinsic base region. Next, on the surface of the region of the N-type silicon substrate where the P-type intrinsic base region is formed a masking material consisting of a first silicon oxide film of thickness of about 50 nm is formed. Next, an undoped polycrystalline silicon film and a solid phase diffused material consisting of, for example, a BSG film (with boron concentration of about 1.times.10.sup.20 cm.sup.-3) are deposited in sequence allover the surface. Following that, a P.sup.+ -type extrinsic base region (with junction depth of about 0.5 .mu.m) and a P-type intrinsic base region (with junction depth of about 0.3 .mu.m) are formed by annealing at 950.degree. C. for 30 min. As a result of the annealing, the undoped polycrystalline silicon film is converted to a P.sup.+ -type polycrystalline silicon film. Next, after removal of the solid phase diffused material an interlayer insulating film consisting of a second silicon oxide film is formed allover the surface.
Next, the interlayer insulating film and the P.sup.+ -type polycrystalline silicon film are etched in sequence by a two stage RIE that uses that uses photoresist films, a base lead-out electrode consisting of a P.sup.+ -type polycrystalline silicon film is formed, and at the same time a window is formed in the region where an emitter opening is to be formed. Since the masking material functions as a stopper in the etching of the P.sup.+ -type polycrystalline silicon film, the surface of the N-type silicon substrate will not be exposed to this etching, and the generation of faults, contamination, damages or the like in this part can be avoided.
Next, a third silicon oxide film is deposited allover the surface. Following that, the silicon oxide film is etched back by an RIE, and an emitter opening having the silicon oxide film as a spacer is formed. Next, an emitter lead-out electrode consisting of an N.sup.+ -type polycrystalline silicon film is formed, and an N.sup.+ -type emitter region is formed by heat treatment. Following that, an opening formed in the interlayer insulating film, and a base electrode is formed.
According to this fabrication method, a P-type intrinsic base region is formed by boron from the BSG film which passed the polycrystalline silicon film and the mask material. Because of this, when the impurity concentration of the P-type intrinsic base region is high, the parasitic base resistance can be reduced but the base width is increased (in other words, the junction depth of the P-type intrinsic base region becomes large) and the cut-off frequency (f.sub.T) cannot be raised so that the method is not suitable for increasing the operating speed. On the other hand, when the impurity concentration of the P-type intrinsic base region is low, the parasitic base resistance cannot be reduced, and the aforementioned first issue cannot be settled.